1. Field of the Invention
The present invention relates to high speed, high processing gain, PN spread spectrum acquisition systems. More particularly, the present invention relates to a novel parallel correlator used for acquisition to increase the search speed of acquisition by effectively slowing the novel parallel correlator speed down to a fraction of the speed of the other acquisition circuitry.
2. Description of the Prior Art
In our co-ending U.S. application Ser. No. 08/170,604 filed Dec. 21, 1993 concurrent herewith, now U.S. Pat. No. 5,414,730, there is shown and described an Asynchronous Sample Data Demodulation System having a novel correlator used for parallel despreading a received PN coded signal. This novel correlator despreaded all of the PN coded signals in a burst of information and stores soft decisions used to demodulate and track the received signal.
The correlator in this co-pending application was found to be limited by a speed no greater than about one-third the operational speed of the analog receiver and its associated analog to digital converter.
If the operational speed of the converter of the co-pending application system could be increased by a factor of three to five times without an appreciable cost and complexity, then the processing gain of the system could be increased directly proportionally to the factor of the speed increase of the correlator. Thus, it is highly desirable to provide a high performance acquisition system which includes a novel correlator whose effective speed of operation can be increased by an integer or factor greater than two.
It is a primary object of the present invention to provide a novel acquisition system for PN coded signals.
It is a primary object of the present invention to provide a high speed novel acquisition system for use in acquiring burst signals or continuous signals with or without a preamble or header.
It is a primary object of the present invention to provide a novel correlator which comprises a plurality of identical parallel correlators arranged to correlate specific portions of an N chip signal which portions together span a contiguous the N chip signal.
It is a primary object of the present invention to provide apparatus for demuxing received PN coded signal and demuxing the replica PN coded signal to provide a plurality of PN replica codes that are synchronized with each other.
It is a primary object of the present invention to provide a plurality of parallel correlators each operating at a fraction of the PN code chip rate whose outputs are summed to provide an effective output at the desired PN code chip rate.
According to these and other objects of the present invention, there is provided an apparatus for receiving and acquiring a high performance, high speed PN coded signal having a front end receiver for converting received analog signals into a digital format and for demuxing the received digital signals. The output of the demuxed digital signals are coupled to a plurality of correlators, each of which is provided with a demuxed replica PN code value synchronized with the received demuxed PN coded signals. The sum of sets of correlators are coherently accumulated over a data symbol duration and further these signals are noncoherently accumulated over a plurality of data symbol times to achieve a high enough signal to noise ratio to achieve detection of lock on of the PN replica coded signal to the received signal.